1. Field of the Invention
The present invention relates to a semiconductor device having a dummy gate and, more particularly, to a semiconductor device including a plurality of MOS transistors and a dummy gate disposed between adjacent MOS transistors.
2. Description of the Related Art
A ring oscillator in a semiconductor device is such that an odd number of inverters are connected or cascaded in a loop. If the inverter is configured by a CMOS gate configured on a semiconductor substrate, such an oscillator circuit can be formed in a small area and is suitably employed in a clock circuit of the semiconductor device. The operational speed of the oscillator circuit has been increased steadily and its oscillation frequency is about to exceed 1 GHz.
While the operational speed of the oscillator circuit has been thus improved, there has occurred a problem in that a desired operational speed cannot be obtained even with the case where a required voltage is applied to the ring oscillator. This means that the parasitic capacitance between conductive layers and between interconnects cannot be ignored in the recent semiconductor devices which have a smaller and smaller design rule. More specifically, it is generally considered that the parasitic capacitance largely contributes to the reduction in the operational speed. In order to cope with the above problem, JP-2000-216263A describes a semiconductor device formed such that the overlapping area between a diffused region and interconnects to be formed above the diffused region is reduced.
The semiconductor device described in the above publication can reduce the parasitic capacitance between the diffused region and the interconnects, to thereby prevent reduction in the operational speed. However, along with an increase in the operational speed of the recent oscillator circuit, the parasitic capacitance between the interconnects and the diffused region, in addition to the parasitic capacitance between a plurality of conductive layers and the parasitic capacitance between the interconnects within the semiconductor device, has become the critical factor that prevents the increase in the operational speed. Therefore, it is necessary to reduce the parasitic capacitance other than that between the interconnects and diffused region, in order to improve the operational speed of the semiconductor circuit.
Further, along with the increase in the operational speed of the semiconductor device, the oscillation frequency varies widely in some semiconductor devices to cause another problem. This problem is not described in the above publication.
The present inventor has conducted a study for realizing a semiconductor device designed to have an oscillation circuit, achieving a high-speed circuit operation by using the oscillation circuit, and yet capable of suppressing variation in the oscillation frequency of the oscillation circuit. As an example of the oscillator circuit, the present inventor has made a study on the ring oscillator having a circuit configuration shown in FIG. 8.
A ring oscillator 60 is such that an odd number of inverters 61 are cascaded in a loop. The logical value of the output of each inverter is inverted after passing the each inverter within the loop, with the result that the ring oscillator oscillates at a predetermined frequency depending on the number of the inverters 61. Each of the inverters 61 is configured by a CMOS gate.
FIG. 9 is a top plan view of a semiconductor device, showing a PMOS section in the CMOS gates of the ring oscillator 60. FIG. 10 is a sectional view taken along line X-X in FIG. 9. The semiconductor device 70 includes a semiconductor substrate 11 and gate electrodes 12 arranged at a constant pitch or constant interval on the semiconductor substrate 11. Each of the gate electrodes 12 is made of polysilicon. On both sides of the gate electrodes 12, diffused regions 13 into which p-type impurities are implanted are formed in the surface region of the semiconductor substrate 11. Each of the diffused regions 13 serves as a source 13a or drain 13b of the transistor 14. Starting from an edge of the semiconductor substrate 11, the diffused regions 13 are arranged in the order of source 13a, drain 13b, source 13a, drain 13b, . . . , drain 13b and source 13a, which is disposed in the vicinity of the other edge of the semiconductor substrate.
All the source regions 13a are connected via interconnects (not shown) to the common power source line. A pair of gate electrodes 12 on both sides of each drain region 13b is connected via an interconnect (not shown) to the drain region 13b of the precedent stage of the ring oscillator. A single transistor 14 is configured by a drain region 13b, a pair of source regions 13a on both sides of the drain region 13b, and a pair of gate electrodes 12 formed on the semiconductor substrate 11 at the portion between the source regions 13a and drain region 13b. The depicted portion of the semiconductor device 70 includes three transistors 14-1, 14-2, and 14-3. These transistors 14-1 to 14-3 correspond to the PMOS transistors in the CMOS gates configuring the inverters 61-1 to 61-3 shown in FIG. 8.
A first interlevel dielectric film 15 is formed on the semiconductor substrate 11 to cover the gate electrode 12. A first-layer source contact 16a and a first-layer drain contact 16b are formed to penetrate the first interlevel dielectric film 15. The first-layer source contact 16a reaches the source 13a, whereas the first-layer drain contact 16b reaches the drain region 13b. On the first interlevel dielectric film 15, there are formed a first-layer source line 17a and a first-layer drain line 17b. The first-layer source line 17a is connected to the first-layer source contact 16a, whereas the first-layer drain line 17b is connected to the first-layer drain contact 16b. 
A second interlevel dielectric film 18 is formed on the first interlevel dielectric film 15 to cover the first-layer source line 17a and first-layer drain line 17b. A second-layer source contact 19a and a second-layer drain contact 19b are formed to penetrate the second interlevel dielectric film 18. The second-layer source contact 19a reaches the first-layer source line 17a, whereas the second-layer drain contact 19b reaches the first-layer drain line 17b. 
On the second interlevel dielectric film 18, there are formed a second-layer source line 20a and a second-layer drain line 20b. The second-layer source line 20a is connected to the second-layer source contact 19a, whereas the second-layer drain line 20b is connected to the second-layer drain contact 19b. A third interlevel dielectric film 21 is formed on the second interlevel dielectric film 18 to cover the second-layer source line 20a and second-layer drain line 20b. 
Each of the interconnects 17a, 17b, 20a, and 20b is made of, e.g., aluminum, and each of the contacts 16a, 16b, 20a, and 20b is made of e.g., polysilicon. The gate electrode 12 and second-layer drain line 20b extend toward the front side of FIG. 10, whereas the second-layer source line 20a extends toward the rear side of FIG. 10.
As a first investigation, the present inventor has studied the parasitic capacitance between conductive layers and between interconnects that prevent an increase in the operational speed of the semiconductor device 70. FIG. 11 shows one of the transistors 14 shown in FIG. 10 in an enlarged view. In FIG. 11, the interlevel dielectric films 15, 18, and 21 are omitted for depiction, for the sake of simplification. The first-layer source line 17a and first-layer drain line 17b are disposed close to each other, and second-layer source line 20a and second-layer drain line 20b are disposed close to each other, thereby incurring a large parasitic capacitance therebetween. The width of each interconnect is, e.g., 0.30 μm.
In addition, a large parasitic capacitance is incurred between the drain region 13b and gate electrodes 12 on both sides of the drain region 13b, between the drain region 13b and the first-layer drain line 17b, or between the drain region 13b and the second-layer drain line 20b. The parasitic capacitance between the drain region 13b and the second-layer drain line 20b has not been acknowledged heretofore as a significant problem. However, along with the reduction in the design rule and the increase in the operational speed of the semiconductor devices, the parasitic capacitance between the drain region 13b and the second-layer drain line 20b causes a substantive problem. Therefore, it is desired to reduce the above parasitic capacitance in order to improve the operational speed of the semiconductor device.
As a second investigation, the present inventor focused attention on the fact that although a reduction in the width (L) of the gate electrode is generally preferable for a reduction in the parasitic capacitance, an increase in the ratio of the interval of adjacent gate electrodes to the width (L) of the gate electrode, which ratio is referred to as an aspect ratio hereinafter, reduces the controllability for the oscillation frequency. As a first example of the semiconductor device, the present inventor manufactured the semiconductor device 70 of FIG. 9 in which a variety of aspect ratios are selected, with the width L of the gate electrode being as a constant. The width L may be referred to as “L-value” hereinafter, and the L-value in the actual semiconductor device may be referred to as “product L-value”.
Further, as a second example of the semiconductor device, the present inventor manufactured the semiconductor device 70 of FIG. 9 in which the transistors 14-1 to 14-3 are designed as NMOS transistors. Similarly, a variety of aspect ratios were selected in this semiconductor device, with the L-value in the product being as a constant. The relationship between the L-value and the aspect ratio was examined in the thus manufactured semiconductor devices.
FIG. 12 shows the result of the investigation where the aspect ratio is plotted on abscissa, and the product L-value is plotted on ordinate. The depicted curved (i) represents the average of the results in the first example of the semiconductor device and the depicted curved (ii) represents the average of the results in the second example of the semiconductor device. The origin for the curve (i) is shifted upward in the vertical direction for a better understanding. It is to be noted that a positive-type resist was used for exposure during forming the mask pattern of the gate electrode.
As represented by arrows in FIG. 12, increase of the aspect ratio reduces the L-value and, at the same time, increases the range of variation in the product L-value. A larger range of variation in the product L-value causes a larger disturbance in the oscillating waveform output from the oscillator circuit, resulting in a larger range of variation in the oscillation frequency. Therefore, it is desired to reduce the aspect ratio in order to increase the controllability for the circuit operation of the semiconductor device. The experiment made by the present inventor revealed that it is preferable to reduce the aspect ratio down to less than 4.1 in the semiconductor device having an oscillation frequency higher than 1 GHz.
The cause that the variation in the product L-value increases with the increase in the aspect ratio may be concluded as follows. That is, when resist is being exposed to form a mask pattern of the gate electrodes, a higher aspect ratio of the gate electrodes allows the light reflected by the surrounding area to enter the non-exposure area of the semiconductor wafer. This causes a change in the width of the mask pattern, resulting in a larger range of variation in the product L-value.
As a third investigation, the present inventor focused attention on the fact that the variation in the aspect ratio in the semiconductor device affects the oscillation frequency. A third example of the semiconductor device was manufactured, wherein the semiconductor device was designed as a ring oscillator such as shown in FIG. 8, and included PMOS transistors shown in FIG. 9 and NMOS transistors in the CMOS gates, the NMOS transistors having a configuration similar to that of the transistors 14-1, 14-2, and 14-3 shown in FIG. 9. The intervals D1 to D3 between adjacent gate electrodes 12 were selected at 0.8 μm. The L-value of each of the gate electrodes 12 was designed at a constant in the PMOS transistors and NMOS transistors.
Further, a fourth example of the semiconductor device was manufactured similarly to the third example except that the intervals D1 to D3 between the gate electrodes 12 are designed at 0.7 μm, 0.8 μμm, and 0.9μμ.
The third and fourth examples of the semiconductor devices were operated and the oscillation period was examined in each device. Curved lines (i) and (ii) of FIG. 13 represent the waveforms of the oscillating signals in the third and fourth examples, respectively, of the semiconductor device. In FIG. 13, the oscillation period of the third example of the semiconductor device is about equal to a design value; whereas the oscillation period of the fourth example of the semiconductor device is longer than the design value.
Examination was made to determine the cause of difference between the oscillating period of the ring oscillators in the third and fourth examples of the semiconductor device thus manufactured and the design oscillation period. In the third example of the semiconductor device, the aspect ratio was constant, whereby the product L-value was approximately equal to the designed L-value; whereas in the fourth example of the semiconductor device, the aspect was not constant, whereby the product L-value varied widely. As a result, in the fourth example of the semiconductor device, the controllability for the circuit operation was reduced to cause the oscillation period to be longer than the design period. Therefore, it is confirmed that the L-value and aspect ratio should be designed to have a constant value in the semiconductor device, in order to increase the controllability for the circuit operation.
In order to increase the intervals between the conductive layers and between the interconnects in the conventional semiconductor device shown in FIG. 9, it my be considered that the source regions 13a shared between adjacent two of the transistors 14-1, 14-2, and 14-3 be separated to thereby isolate the transistors 14-1, 14-2, and 14-3 as individual transistors. In this configuration, however, flexibility in the arrangement of the gate electrodes is small so that it is difficult to make the interval or pitch between the gate electrodes constant. In addition, the above separation increases the surface area of the transistors 14-1, 14-2, and 14-3.